The present invention relates to a semiconductor memory device and, more particularly, a technique effective for use in a semiconductor memory device used in a plurality of modes by using a common chip as a base.
Bonding option is effective means by which products adapted to the market trend can be supplied without a delay by storing products subjected to a preceding process and realizing products according to a selected product specification by bonding in a following process. In a dynamic RAM (Random Access Memory) (hereinbelow, simply called a DRAM), the bonding option is used for selection of a word configuration (bit configuration) such as xc3x974, xc3x978, or xc3x9716 configuration. A metal option technique of changing a circuit function by selective layout of metal wires is also known.
Japanese Unexamined Patent Application No. Hei 10(1998)-302465 (corresponding to U.S. Pat. No. 6,060,916) discloses a technique of enabling a single data rate (SDR) mode or a double data rate (DDR) mode to be selected on a memory chip in accordance with an output signal of a mode selection unit 301 constructed by either a photo mask or fuse.
Japanese Unexamined Patent Application No. Hei 11(1999)-203868 (corresponding to U.S. Pat. No. 6,094,375) discloses a technique of selecting the SDR mode or the DDR mode in accordance with an output signal of a mode selection signal generating unit constructed by a fuse, accessing a memory cell by a group of column addresses in the SDR mode, and accessing a memory cell by the remaining column addresses except for a specific column address in the DDR mode.
Japanese Unexamined Patent Application No. Hei 11(1999)-213668 (corresponding to U.S. Pat. No. 6,151,271) discloses a technique of programming a DDR or SDR operation mode of a synchronous DRAM by a manufacturer or user, holding a mode selection signal in a mode register, outputting the mode selection signal from the mode register to a control signal generating unit, and outputting, as an internal clock, either a first clock having a cycle of an integral multiple of that of an external system clock and a second clock having a cycle which is double of the first clock. The DDR or SDR operation mode is fixed by, for example, metal option, mask option, bonding option, or a fuse by a manufacturer in a manufacturing process.
Japanese Unexamined Patent Application No. 2000-67577 discloses a synchronous semiconductor memory device in which, in a SDR SDRAM operation mode, an input/output buffer circuit operates synchronously with an external clock signal and, in a DDR SDRAM operation mode, an internal clock signal of a frequency twice as high as that of the external clock signal is generated, and the input/output buffer circuit operates synchronously with the internal clock signal.
Japanese Unexamined Patent Application No. 2000-40398 (corresponding to U.S. Pat. No. 6,151,272) discloses a technique of testing a DDR synchronous DRAM integrated circuit device by a low-speed tester by activating a SDR mode signal to operate the DDR synchronous DRAM integrated circuit device in a SDR mode.
Japanese Unexamined Patent Application No. Hei 11(1999)-191292 (corresponding to U.S. Pat. No. 6,011,751) discloses a synchronous semiconductor memory device capable of selectively generating a burst address signal in a linear mode or an interleave mode so as to be selectively adapted to the SDR operation mode or the DDR operation mode by selecting either a configuration in which multiplexers are provided at ante stages of a plurality of registers, and a connection relation of the registers is selected, thereby incrementing an address or a configuration of selecting a signal obtained by inverting a register output by a multiplexer.
In order to be adapted to a high speed memory system of the next generation, a DDR-SDRAM (Double Data Rate Synchronous DRAM) is proposed. Since the DDR-SDRAM is obtained by improving an SDRAM (Synchronous DRAM) in order to achieve higher performances, the DDR-SDRAM and the SDRAM have many common portions from a circuit viewpoint. The inventors of the present invention paid attention on the commonality between the SDRAM and the DDR-SDRAM and examined the possibility of improving developed TAT, reduction in manufacturing cost as a total, and so on by realizing formation of the SDRAM and the DDR-SDRAM on the same chip.
During the examination, a large difference was found between an input interface in a final product specification of the DDR-SDRAM and that of the SDRAM. Specifically, in the SDRAM, a mask signal is input in response to a command input. On the other hand, in the DDR-SDRAM, a mask signal is input in response to a write signal. Regarding such inputs of the mask signals, not only just signal input timings but also input capacitances of signal pins seen from the host side have to be made different from each other. For example, the standard of the input capacitance of a data mask signal pin in the SDRAM is set in a range from 2.5 to 3.8 pF which is the same as that of a command pin such as /CS or /RAS and that of an address pin. In contrast, in the DDR-SDRAM, it is set in a range from 4.0 to 5.5 pF which is the same as that of a data pin. Consequently, there is no common area of an input capacitance value between the SDRAM and DDR-SDRAM. In addition to the difference in the input capacitances, the input timings are also different from each other as described above. Consequently, internal timing adjustment is necessary. It was made clear by the inventors that, when two kinds of circuits for the DDR-SDRAM and the SDRAM are mounted on the same chip, a problem such that the circuit scale is enlarged occurs.
An object of the invention is to provide a semiconductor memory device having an input circuit adapted for two kinds of input specifications while suppressing enlargement of the circuit scale. Another object of the invention is to provide an SDRAM and a DDR-SDRAM formed by using a common chip. The above and other objects and novel features of the invention will become apparent from the description of the specification and the appended claims.
A representative one of inventions disclosed in the application will be briefly described as follows. In a semiconductor memory device in which an access to a memory cell is designated according to a command, and a common data terminal is used as an input terminal to which a write signal to the memory cell is input and an output terminal from which a read signal from the memory cell is output, a first input circuit having input capacitance corresponding to the input terminal to which the command is input and a second input circuit having input capacitance corresponding to the data terminal are formed. A mask signal for checking the write signal input from the data terminal is input by either the first or second input circuit by a bonding option technique.
Another representative one of inventions disclosed in the application will be briefly described as follows. In a semiconductor memory device in which an access to any of the memory cells is designated according to a command, and a common data terminal is used as an input terminal to which a write signal to the memory cell is input and an output terminal from which a read signal from the memory cell is output, an input circuit having addition capacitance corresponding to a difference between first input capacitance corresponding to the input terminal to which the command is input and second input capacitance corresponding to the data terminal is formed. By a metal option technique, the addition capacitance is not connected in a configuration of inputting the mask signal in response to the command, or the addition capacitance is connected to the input circuit in a configuration of inputting the mask signal in response to the write signal.